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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
FEATURES
* 20 LVCMOS outputs, 7 typical output impedance * 1 differential clock input pair * CLK, nCLK supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency up to 250MHz * Translates any differential input signal (LVPECL, LVHSTL, LVDS) to LVCMOS levels without external bias networks * Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input * Bank enable logic allows unused banks to be disabled in reduced fanout applications * Output skew: 200ps (maximum) * Bank skew: 150ps (maximum) * Part-to-part skew: 650ps (maximum) * Multiple frequency skew: 250ps (maximum) * 3.3V or mixed 3.3V input, 2.5V output operating supply modes * 0C to 70C ambient operating temperature * Other divide values available on request
ICS8702
GENERAL DESCRIPTION
The ICS8702 is a low skew, /1, /2 Differential-toLVCMOS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
,&6
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously. The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK DIV_SELA
1 0
PIN ASSIGNMENT
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
1 0
/1 /2
QAO - QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
QB0 - QB4
DIV_SELB
1 0
QC0 - QC4
DIV_SELC
1 0
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8702
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
DIV_SELA DIV_SELB CLK nCLK VDD BANK_EN0 GND BANK_EN1 VDD nMR/OE DIV_SELC DIV_SELD
DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic
48-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View
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1
REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Type Power Description Output supply pins. Connect to 3.3V or 2.5V.
ICS8702
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 1 2 22 21 13 14 23 24 17, 19 15 Name VDDO
GND VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK nCLK DIV_SELD DIV_SELC DIV_SELB DIV_SELA BANK_EN1, BANK_EN0 nMR/OE
Power Power Output Output Output Output Input Input Input Input Input Input Input Input
Output power supply. Connect to ground. Positive supply pins. Connect to 3.3V. Bank A outputs. 7W typical output impedance. Bank B outputs. 7W typical output impedance. Bank C outputs. 7W typical output impedance. Bank D outputs. 7W typical output impedance. Pulldown Non-inver ting differential clock input. Pullup Pullup Pullup Pullup Pullup Pullup Pullup Inver ting differential clock input. Controls frequency division for Bank D outputs. LVCMOS interface levels. Controls frequency division for Bank C outputs. LVCMOS interface levels. Controls frequency division for Bank B outputs LVCMOS interface levels. Controls frequency division for Bank A outputs. LVCMOS interface levels. Enables and disables outputs by banks. LVCMOS interface levels.
Asynchronous master reset. Resets clock dividers. Enables and disable all outputs. LVCMOS interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 51 51 VDD = VDDO = 3.465V 7 15 Maximum 4 Units pF KW KW pF
W
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Outputs QC0 - QC4 QD0 - QD4 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Enabled Hi Z Enabled Enabled Hi Z Hi Z Hi Z Hi Z Enabled Hi Z Enabled Enabled
ICS8702
TABLE 3A. CONTROL INPUT FUNCTION TABLE
nMR/OE 0 1 1 1 1 1 1 1 1 Inputs BANK_EN1 BANK_EN0 X X 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0 - QA4 Hi Z Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled QB0 - QB4 Hi Z Hi Z Enabled Enabled Enabled Hi Z Enabled Enabled Enabled Qx Frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
TABLE 3B. CLOCK INPUT FUNCTION TABLE
nMR/OE 1 1 1 1 1 Inputs CLK 0 1 0 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Qx0 thru Qx4 LOW HIGH LOW HIGH HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
1 Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting NOTE 1: Please refer to the Application Information section on page 11, Figure 8, which discusses wiring the differential input to accept single ended levels.
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C
ICS8702
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol VIH Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE Test Conditions Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
5
A
IIL
Input Low Current
VDD = 3.465V, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA
-150
A
VOH VOL
Output High Voltage Output Low Voltage
2.6 0.5
V V
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Test Conditions CLK nCLK CLK nCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.8 1.3 2.4 1.3 Minimum Typical Maximum 150 5 Units A A A A V V V
ICS8702
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
DCM, LVHSTL, LVDS, SSTL Levels 0.31 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% f 200MHz 280 280 tCYCLE/2 - 0.5 2 2.2 Test Conditions Minimum Typical Maximum 250 3.5 150 200 250 650 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns ns ns ns
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc
tCYCLE/2
f = 200MHz 2.5 Output Enable Time; tEN f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA
ICS8702
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE Test Conditions Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
5
A
IIL
Input Low Current
VDD = 3.465V, VIN = 0V VDD = 3.135V VDDO = 2.375V IOL = -27mA VDD = 3.135V VDDO = 2.375V IOL = 27mA
-150
A
VOH
Output High Voltage
1.9
V
VOL
Output Low Voltage
0.5
V
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.8 1.3 2.4 1.3 Minimum Typical Maximum 150 5 Units A A A A V V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
DCM, LVHSTL, LVDS, SSTL Levels 0.31 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Test Conditions f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% f 200MHz f = 200MHz 280 280 tCYCLE/2 - 0.5 2 Minimum 2.3 Typical Maximum 250 3.6 150 200 250 700 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns ns ns ns
ICS8702
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc tEN
tCYCLE/2 2.5
Output Enable Time; f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
ICS8702
PARAMETER MEASUREMENT INFORMATION
1.65V5%
VDD, VDDO Qx
SCOPE
LVCMOS
GND
-1.65V5%
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
2.05V5% 1.25V5%
VDD
VDDO
SCOPE
LVCMOS
GND
Qx
-1.25V5%
FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
V DD
ICS8702
nCLK V CLK
PP
Cross Points
V
CMR
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
V
Qx
DDO
2
V
Qy
DDO
2 tsk(o)
FIGURE 3 - OUTPUT SKEW
PART 1 Qx
V
DDO
2
PART 2 Qy
V
DDO
2 tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
70% 70% V 30% 30% t t
AND
SWING
ICS8702
Clock Inputs and Outputs
R
F
FIGURE 5 - INPUT
OUTPUT RISE
AND
FALL TIME
nCLK CLK
V
QAx, QBx, QCx, QDx
DDO
2 tp
LH
FIGURE 6 - PROPAGATION DELAY
V
QAx, QBx, QCx, QDx
DDO
2 Pulse Width t
PERIOD
FIGURE 7 - odc & tPERIOD
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR APPLICATION INFORMATION
ICS8702
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER CONSIDERATIONS
For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer.
DRIVER TERMINATION
For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination.
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR RELIABILITY INFORMATION
ICS8702
TABLE 7. JAVS. AIR FLOW TABLE
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8702 is: 1822
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
ICS8702
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
q
ccc
Reference Document: JEDEC Publication 95, MS-026
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Marking ICS8702BY ICS8702BY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
ICS8702
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8702BY ICS8702BY-T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8702BY
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REV. C NOVEMBER 28, 2001
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Revised IDD row from 70mA Maximum to 95mA Maximum. Revised IDD row from 70mA Maximum to 95mA Maximum. Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum. Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum. Added Power Dissipation and Driver Termination notes. Date 8/2/01
ICS8702
Rev B
C
Table 4A 4D 4B 4E
Page 4 6 4 6 11
11/28/01
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REV. C NOVEMBER 28, 2001

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